ESD and Latch-Up Testing

ESD and Latch-Up testing of electronic components is an expensive part of the design and manufacturing of new products. Increased integration and smaller device geometries increase the risk of device failure due to ESD (Electrostatic Discharge). If those failures happen in the field it will significantly effect customer satisfaction and reliability.

Types of ESD and Latch-Up Testing

EAG is an active participant in many industry standards organizations including ESDA and JEDEC. We test to the latest AEC, JEDEC, ESDA and Military Standards. EAG believes that Standards alone are not enough and we offer additional services that will help you to narrow down failures.

• Human Body Model (HBM):
  The HBM model simulates the direct transfer of electrostatic charge, from the human body, to a test device. A 100pF capacitor is discharged through a switching component and a 1.5 Kohm series resistor. This is currently the most requested industry model, for classifying device sensitivity to ESD.
  • JESD22-A114 (JEDEC standard), MIL-STD-883, Method 3015.7 (Department of Defense Test Method Standard),
    AEC-Q100-002 (Automotive Electronics Council),
    ESD STM 5.1-1998 (ESD Association Standard Test Method)
• Machine Model (MM):
  The machine model module emulates the rapid direct transfer of electrostatic charge, from a charged conductive object, such as a metallic tool or fixture, to a test device. This model consists of a discharged 200pF capacitor, with no series resistor.
  • JESD22-A115 (JEDEC Standard), AEC-Q100-003,
    ESD STM 5.2-1999
• Charged Device Model (CDM):
  During standard packaging, assembly, and automated processing, integrated circuits may be exposed to rapid electrostatic charge transfer. Typical device triboelectrification occurs during frictional sliding and then rapid discharge via contact with a conductive object. During CDM testing, the device under test is rapidly charged and discharged through a ground plane.
  • JESD22-C101 (JEDEC Standard),
    ESD STM 5.3.1-1999
• Latch-Up:
  Latch-up testing is performed to determine the device latch-up susceptibility. It is based on JESD78 at the customer’s specified current levels and temperatures up to 150^oC.
  • JESD78 (JEDEC Standard),
    AEC-Q100-004 for LU
• Transmission Line Pulse (TLP):
  • ESDA SP5.5-2003,
    ESD Test Chip Evaluation

The ESD Total Solution

At EAG, we have established a Center of Excellence for ESD and latch-up testing. EAG works with clients worldwide to create the knowledge exchange that builds successes in the design of next generation integrated circuits. Our engineers use their industry leading knowledge and years or real world experience of the latest semiconductor technologies, circuit design, and device physics to optimize our customer’s ESD and latch-up results.

When you choose the EAG ESD Total Solution, you will be working together with recognized experts in the field of ESD and latch-up testing. We are committed to providing our customers with the most up-to-date testing methodologies, along with technical interpretation of the test data and accurate assessment of the results.

Tester Specifications

• Humidity controlled lab
• Best in Class ESD and latch-up tester equipment
• Up to 2304 pins for HBM, MM & Latch-up
• 256,000 state vector preconditioning at multiple voltage levels for latch-up testing
• Up to 125°C ambient temperature capability for latch-up testing
• Ability to provide pre and post CDM curve traces
• CDM testing is performed under nitrogen pur

Over 300 Test Fixtures & Sockets

• Universal BGA boards for most 1.27mm, 1.0mm, 0.8mm, 0.65mm, 0.5mm, and 0.4mm packages
• If we do not have a test fixture for your package, we can have boards designed and built.
• Our test boards are designed and built to provide less inductance and accurate pulses to your components.